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 Post subject: O57T: Processor - TMS570
PostPosted: Sat Feb 28, 2015 1:47 pm 
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TMS570 is an ARM Cortex-R architecture processor. It is oriented more towards real-time processing than Cortex-M and as such various aspects about its operation have been changed so its operation is more deterministic, which I interpret as being more predictable and therefore more reliable.

What has drawn me to this chip type-family are the facts that it is automotive use qualified, designs and use situations can, when done properly, be certified against ISO and other related safety standards, it's ADC are 5v compatible, and TI's N2HET module- a high resolution timer; TMS570LS1224 as shown on the kit below has two. This module is a high-resolution timer capable of performing operations in the time and angle domains.

Attachment:
med_launchxl2-tms57012_jmi_0011_sm.jpg
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Texas Instruments provides extensive documentation for this chip, most of which can be accessed from here. Documentation for the chip, overall chip family and device errata as well as links to the development environment, supporting tools and more information are available from that link.

From the "family documentation" for this chip, here section 23.1.1 page 1032 (yep, lots of pages):
"The N2HET is a fifth-generation Texas Instruments (TI) advanced intelligent timer module. It provides an enhanced feature set compared to previous generations.
This timer module provides sophisticated timing functions for real-time applications such as engine management or motor control. The high resolution hardware channels allow greater accuracy for widely used timing functions such as period and pulse measurements, output compare, and PWMs.
The reduced instruction set, based mostly on very simple, but comprehensive instructions, improves the definition and development cycle time of an application and its derivatives. The N2HET breakpoint feature, combined with various stop capabilities, makes the N2HET software application easy to debug."

To clarify that a bit, the N2HET module is actually a dedicated processor whose specific functions are to respond to external events and generate events based on very specific timing requirements. One use case may be for railroad locomotive power and signaling, another may be responding to signals and signals to drive a multi-phase electric motor, others may be reading wheel speeds for an adaptive traction control system, adaptive power steering assist or an engine control system.

A little deeper run down of the processor:
Quote:
High-Performance Automotive-Grade Microcontroller for Safety-Critical Applications Dual CPUs Running in Lockstep
ECC on Flash and RAM Interfaces
Built-In Self-Test for CPU and On-chip RAMs
Error Signaling Module with Error Pin
Voltage and Clock Monitoring
ARM® Cortex™ – R4F 32-Bit RISC CPU 1.66 DMIPS/MHz with 8-Stage Pipeline
FPU with Single- and Double-Precision
12-Region Memory Protection Unit
Open Architecture with Third-Party Support
Operating Conditions Up to 180-MHz System Clock
Core Supply Voltage (VCC): 1.14 to 1.32 V
I/O Supply Voltage (VCCIO): 3.0 to 3.6 V

Integrated Memory 1.25MB of Program Flash with ECC
192KB of RAM with ECC
64KB of Flash for Emulated EEPROM with ECC
16-Bit External Memory Interface (EMIF)
Common Platform Architecture Consistent Memory Map Across Family
Real-Time Interrupt (RTI) Timer (OS Timer)
128-Channel Vectored Interrupt Module (VIM)
2-Channel Cyclic Redundancy Checker (CRC)
Direct Memory Access (DMA) Controller 16 Channels and 32 Control Packets
Parity Protection for Control Packet RAM
DMA Accesses Protected by Dedicated MPU

Frequency-Modulated Phase-Locked Loop (FMPLL) with Built-In Slip Detector
Separate Nonmodulating PLL
IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight™ Components
Advanced JTAG Security Module (AJSM)
Trace and Calibration Capabilities Parameter Overlay Module (POM)

Sixteen General-Purpose Input/Output (GPIO) Pins Capable of Generating Interrupts
Enhanced Timing Peripherals for Motor Control 7 Enhanced Pulse Width Modulator (ePWM) Modules
6 Enhanced Capture (eCAP) Modules
2 Enhanced Quadrature Encoder Pulse (eQEP) Modules

Two High-End Timer (N2HETs) Modules N2HET1: 32 Programmable Channels
N2HET2: 18 Programmable Channels
160-Word Instruction RAM with Parity Protection Each
Each N2HET Includes Hardware Angle Generator
Dedicated Transfer Units (HTU) on N2HETs

Two 10- and 12-Bit Multibuffered Analog-to-Digital Converter (MibADC) Modules ADC1: 24 Channels
ADC2: 16 Channels Shared with ADC1
64 Result Buffers with Parity Protection Each

Multiple Communication Interfaces Three CAN Controllers (DCANs) 64 Mailboxes with Parity Protection Each
Compliant to CAN Protocol Version 2.0A and 2.0B

Inter-Integrated Circuit (I2C)
Three Multibuffered Serial Peripheral Interface (MibSPI) Modules 128 Words with Parity Protection Each
8 Transfer Groups

Up to Two Standard Serial Peripheral Interface (SPI) Modules
Two UART (SCI) Interfaces, One with Local Interconnect Network (LIN 2.1) Interface Support

Packages
144-Pin Quad Flatpack (PGE) [Green]
337-Ball Grid Array (ZWT) [Green]

_________________
/me goes off to the corner feeling like Jerry Springer with a mullet.

My O5E candidate: 1982 Honda CX500TC motorcycle.


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